1. Field of the Invention
The invention relates generally to the vertical semiconductor power devices. More particularly, this invention relates to configurations and manufacturing methods for providing a self-aligned accumulation-mode field-effect transistor (AccuFET) with ultra-small pitch to achieve a high power density with minimized parasitic bipolar actions for high device ruggedness while simplified manufacturing process to produce low cost semiconductor power devices suitable for implementation with both N and P-channel configurations.
2. Description of the Prior Art
Conventional manufacturing technologies and device configuration encounter several technical difficulties when the cell pitch of the trench-DMOS devices is further reduced. Specifically, the device structure is weakened due to the increase of the parasitic bipolar actions. As the cell pitch becomes smaller, it is difficult to form effective body contact with low resistance. The increase in the resistance of the body region due to the difficulties of smaller dimensions available for the contact areas further results the increased parasitic bipolar current gain. For NMOS devices, the increased parasitic bipolar actions weakened the devices and prevent the devices to achieve a high UIS rating.
A device implemented with the accumulation mode field effect transistors has the benefits that there is no parasitic bipolar structure because there are no P-body regions for the NMOS device. For an N-channel device, an enhancement mode of operation can be achieved by using a P+ doped gate combined with appropriately selected epitaxial doping and gate to gate spacing to achieve a fully depleted channel region with no conduction when the gate-to-drain voltage Vgs is at zero volt. Baliga et al. disclosed the configuration of an AccuFET device in an article entitled “The Accumulation-Mode Field-effect Transistor: A new Ultra Low On-Resistance MOSFET” (IEEE EDL, August 1992, Page 427).
Additional disclosures for the AccuFET devices were made in different U.S. Patents, such as U.S. Pat. No. 4,903,189 with a device configuration shown in FIG. 1A. Another device configuration shown in FIG. 1B is disclosed in U.S. Pat. No. 5,581,100. Furthermore, U.S. Pat. No. 5,844,273 discloses different AccuFET device configurations shown in FIG. 1C. However, these disclosures for manufacturing the AccuFET devices still have limitations that a small cell pitch with short channel vertical AccuFET configuration cannot be achieved. Additionally, for certain applications, an integration of an efficient body structure within the device with a negatively biased drain is desirable. However, conventional configurations and methods of manufacturing the AccuFET devices cannot satisfy such demands.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and methods of manufacturing the AccuFET devices such that the above discussed problems and limitations can be resolved.